Deterministic read disturb counter-based data checking for NAND flash

ABSTRACT

A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device. The non-volatile semiconductor memory device can store data in memory blocks. The solid-state drive controller can, periodically, retrieve counts from a counter table, select a predetermined number of memory blocks corresponding to the lowest counts, and determine an integrity of the stored data in each of the predetermined number of memory blocks. Each count can correspond to a difference between a count limit and a number of read operations performed on one of the memory blocks.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of application Ser. No. 16/186,836filed Nov. 12, 2018, which is a continuation of application Ser. No.15/702,930 filed Sep. 13, 2017, the entire contents of which areincorporated herein by reference.

FIELD OF THE INVENTION

The present disclosure relates to data storage devices and methods formanaging read disturb errors in memory blocks.

BACKGROUND

Solid-state storage devices employing non-volatile semiconductor memorysuch as NAND flash memory typically use block or page read counters asan indicator that checks should be made for memory blocks or pages thatmay be subject to read disturb errors. When a page or block counter,counting up or down, reaches a limit value, the solid-state drive (SSD)controller instigates a check of pages or memory blocks that may beaffected by read disturb errors following the number of reads of thepage or memory block monitored by the counter. Read disturb errors causethe data in neighboring pages within the memory block to change due to aweak programming effect of wordlines adjacent to the page or memoryblock being read.

Typically, block and page counters are employed with programmable limitsbut with no attempt to limit the number of counters that may hit thelimits at any given time. With uncontrolled and unpredictable workloads,the only limit to the number of memory block and page counters that maysimultaneously reach their limit for checking within a period is therate of read commands to the memory, which in fast SSDs could exceed 1million/second. A ‘storm’ occurs in a read disturb counter limit schemewhere large numbers of counters may be allowed to simultaneously reach alimit and the associated likely disturb affected memory blocks must allbe checked at the same time. This gives rise to a variable andunpredictable degradation of the performance of SSD controllers insolid-state storage devices with a direct influence on the performanceseen by a host device. Accordingly, there is a long felt need to avoidthe aforementioned problems.

SUMMARY OF INVENTION

The present disclosure relates to a data storage device comprising anon-volatile semiconductor memory device and an SSD controller,communicatively coupled to the non-volatile semiconductor memory device.The non-volatile semiconductor memory device can store data in memoryblocks. The solid-state drive controller can, periodically, retrievecounts from a counter table, select a predetermined number of memoryblocks corresponding to the lowest counts, and determine an integrity ofthe stored data in each of the predetermined number of memory blocks.Each count can correspond to a difference between a count limit and anumber of read operations performed on one of the memory blocks.

According to one implementation, the period may be dynamically adjustedbased on a rate of arrival of read memory requests at the data storagedevice.

In other implementations, the SSD controller may, in response todetermining that the integrity of the stored data in the memory block isabove a threshold, read the stored data in the memory block, errorcorrect the stored data in the memory block, and transfer the storeddata to a secondary memory block.

In certain implementations, the SSD controller may, in response todetermining that the integrity of the stored data is below thethreshold, set the count corresponding to the memory block in thecounter table to a new limit.

According to some implementations, the SSD controller may determine anaverage number of memory blocks storing data corresponding tointegrities above the threshold.

In some implementations, the predetermined number of memory blocks isgreater than the average number of memory blocks.

According to one implementation, the SSD controller may dynamicallyadjust the predetermined number based on the total hours of operation ofthe data storage device.

In other implementations, the SSD controller may dynamically adjust thepredetermined number based on a rate of arrival of read memory requestsat the data storage device.

In certain implementations, the SSD controller may dynamically adjustthe period and the predetermined number such that none of the countsreaches zero.

According to some implementations, determining the integrity of thestored data in the memory block comprises determining an error level ofthe stored data in at least one memory page of the memory block.

A second aspect of the present disclosure relates to a method ofmanaging memory blocks in a data storage device. The method comprisesstoring data in a plurality of memory blocks. The method also comprisesretrieving counts from a counter table. Each count may correspond to adifference between a count limit and a number of read operationsperformed on one of the memory blocks. Further, the method comprisesselecting, based on the counts, a predetermined number of memory blockscorresponding to a plurality of lowest counts. The method also comprisesdetermining, for each of the predetermined number of memory blocks, anintegrity of the stored data in the memory block.

According to some implementations, the period is dynamically adjustedbased on a rate of arrival of read memory requests at the data storagedevice.

In some implementations, the method further comprises, in response todetermining that the integrity of the stored data in the memory block isabove a threshold, reading the stored data in the memory block, errorcorrecting the stored data in the memory block, and transferring thestored data to a secondary memory block.

In other implementations, the method further comprises, in response todetermining that the integrity of the stored data in the memory block isbelow the threshold, setting the count corresponding to the memory blockin the counter table to a new limit.

According to some implementations, the method also comprises determiningan average number of memory blocks storing data corresponding to aplurality of integrities above the threshold.

In certain implementations, the predetermined number of memory blocks isgreater than the average number of memory blocks.

In other implementations, the method also comprises, dynamicallyadjusting the predetermined number based on the total hours of operationof the data storage device.

According to some implementations, the method further comprises,dynamically adjusting the predetermined number based on a rate ofarrival of read memory requests at the data storage device.

In certain implementations, the method also comprises, dynamicallyadjusting the period and the predetermined number such that none of theplurality of counts reaches zero.

In other implementations, the method further comprises, determining theintegrity of the stored data in the memory block based on determining anerror level of the stored data in at least one memory page of the memoryblock.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects and advantages will be apparent uponconsideration of the following detailed description, taken inconjunction with the accompanying drawings, in which like referencecharacters refer to like parts throughout, and in which:

FIG. 1 shows a schematic representation of data storage device,configured according to one or more embodiments of the presentdisclosure;

FIG. 2 shows a schematic representation of data storage device,according to an embodiment of the present disclosure;

FIG. 3 is a flow diagram of method steps for managing memory blocks in adata storage device, according to an embodiment of the presentdisclosure;

FIG. 4 is a flow diagram of method steps for managing memory blocks in adata storage device, according to an embodiment of the presentdisclosure;

FIG. 5 shows a schematic representation of a count of read operationsfor a memory block, according to an embodiment of the presentdisclosure;

DETAILED DESCRIPTION

FIG. 1 shows a schematic representation of a computing system 100comprising a host system 102 and storage device 104. The host system 102is communicatively coupled to the storage device 104, which is an SSDthat comprising an SSD controller 106 and memory 108. The SSD controller106 comprises read-write-modify circuitry 110 and search functioncircuitry 112 used by the controller 106 to perform deterministicrefresh counting and data checking. The storage device 104 providesnon-volatile storage functionality for use by the host system 102.Storage device 104 may also include other elements not shown, such asnon-volatile semiconductor storage elements, power supply circuitry,indicator light circuitry, temperature sensors, boot circuitry, clockcircuitry, and other circuitry for assisting with various functions.

The SSD controller 106 receives and processes commands from host system102 in order to perform operations on the memory 108. Commands from hostsystem 102 include requests to read or write to locations within thememory 108 and administrative commands, such as commands for queryingthe feature set of storage device 104, commands for formatting memory108, commands for creating and modifying various types of queues,commands for requesting notification of various events, and variousother commands.

Memory 108 is a non-volatile semiconductor memory that stores data atthe request of the host system 102. Memory 108 includes one or morearrays of non-volatile semiconductor-based storage elements, someexamples of which include non-volatile NAND flash memory, non-volatileNOR flash memory, non-volatile DRAM based memory, magnetoresistiverandom-access memory (MRAM), and other types of memory.

FIG. 2 shows a schematic representation of memory 108 comprising a NANDflash memory 202 and counter table 204. NAND flash memory 202 includesmemory blocks 206. Each memory block 206 stores data, and can be writtento, read, and erased by the SSD controller 106 and such activities aretracked and counted using read-write-modify circuitry 110. Counter table204 maintains counts 208 of read operations performed on each memoryblock 206. Counter table 204 can be stored in a DRAM or staticrandom-access memory (SRAM). In other embodiments, NAND flash memory 202can include counter table 204.

Each count 208 provides an indication of the number of read operationsthat have been performed on a corresponding memory block 206. Each count208 is initialized to a predetermined number and decrements after a readoperation is performed on a corresponding memory block 206. The initialvalue for each count 208 is related to the read disturb limit of theNAND flash memory 202. The read disturb limit is the point at which theread error rate exceeds the capability of the SSD controller 106 tocorrect errors in a NAND page. The initial value is selected such thatthe read disturb limit is preferably never reached. The read disturblimit is also related to the technology included in memory 108 as wellas the scale of the fabrication process. As technologies haveprogressed, the effects of read disturb errors has increased. Havingmore charge states in a cell to enable more bits to be stored hasdecreased the limit. In some embodiments, the initial value for eachcount 208 is based on a read disturb limit specified for a particularmemory technology.

Computing system 100 can be used to prevent and protect against readdisturb errors by conducting a search at intervals of T seconds, at arate of 1/T per second, to find the N minimum values and correspondingcount 208 of memory block 206 in a counter table 204. The N minimumvalues correspond to the amount of memory blocks 206 _(N) that have datawith read disturb errors within an interval of T seconds. Counter table204 contains counts 208 for each corresponding to memory blocks 206_(N). Searching for the N values requires a significant amount of systemresources. A large T will require a large N and a small T will require asmall N. T can be dynamically chosen based on the number of readoperations the computing system 100 is performing. Computing system 100can determine an average number of memory blocks 206 _(N) storing datacorresponding to error levels above the threshold within an interval ofT seconds and select the N minimum values to be greater than the averagenumber. The values of N and T will be dependent on the rate of arrivalof read requests from the host system 102. Initial values may be chosenaccording to an expected or specified maximum rate of arrival of readrequests.

The computing system 100 can conduct checks of memory blocks 206potentially affected by errors resulting from read operations performedon the memory blocks 206. The system 100 relies on limiting the numberof memory blocks 206 to be checked by identifying a predetermined numberof check candidates periodically, such that, for any given workload itis highly likely to ensure that so-called checking ‘storms’ do notoccur. The number of checks per second is N/T, so N and T scale in orderfor computing system 100 to maintain a sufficient checking rate. Forexample, N can be 8 or 16 if hardware implemented minimum collection isused. Hardware implemented minimum collection can be made into a bank ofN registers inside a direct memory access search function circuitry 112which searches the counter table 204. If the value of N is known, T canbe determined to maintain a sufficient checking rate for an expected orspecified maximum rate of arrival of read requests. For example, if N is16 and T is 100 ms, 160 checks would be performed per second.

The computing system 100 can conduct checks of memory blocks 206 _(N)with test read operations on one or more memory pages of the memoryblocks, which check for the error levels in data stored in the memoryblock 2061, and then transfers the data in the memory block 2061 to asecondary memory block 2062 if necessary. Secondary block 2062 may be ablock 206 that had been erased and has a corresponding count 208 that isset to an initial value. SSD controller 106 can maintain a pool ofmemory blocks 206 _(N) that are already erased. Transferring the datatakes place on memory blocks with high error levels and presumed likelyto suffer from unrecoverable errors soon. Checking and relocationconsumes memory bus bandwidth and SSD controller resources, causingunpredictable performance in terms of data transfer rates and latenciesif not controlled.

Computing system 100 can limit the checking process to a predictablenumber at the known interval T, which enables the performance andresource degradation to be planned and managed to requiredspecifications. Measurement of workload may enable the checkingparameters, such as rate of checking and number of minimum countercandidates checked, to be varied and/or optimized to realize minimumperformance degradation while still preventing checking ‘storms.’Selection of constant values of N and T can ensure that the workloadimposed by the checking process is deterministic. This, in turn, ensuresthat the effect of the workload on the normal operation of the SSD is tohave a predetermined latency variation and performance throughput in theprocessing of read and write requests from the host system 102.

The selection of N and T is related to the number of IO read operationsreceived by the storage device 104, the size of each IO operation andthe page size of the memory blocks 206 (a memory block 26 being composedof pages, the page being the minimum portion of data which can be readin a NAND flash memory.) Consider a number of 4 KB IO operations persecond of I. For NAND flash memory pages typically of at least 4 KB,each IO operation will cause a maximum of one memory page access. Thetotal number of page (block) counts decremented (or incremented) in Tseconds is (I*T). During this time, a predetermined number N blockcounters 208 are selected and checked, following which the counters 208will be reset to a start limit or set to a new limit. In order for asteady state to exist, every T seconds the number N*BC (where BC is theblock counter value of each of the N blocks) of block counts which arereset or set must equal the number of new block counts received. If N*BCis less than the new block counts received, I*T, then eventually theblock counts may reach a limit (zero if the counts are decremented) inan uncontrolled manner, which is the condition which is to be avoided.Therefore N*BC must be greater or equal to I*T for stable operation. BCmust be less than the read disturb limit RDL, for example RDL minus somesafety margin SM, (RDL−SM). Therefore N must be greater than(I*T)/(RDL-SM).

The above assumes that the IO traffic is spread uniformly (or randomly)across the total blocks 206 of the storage device 104. Non-randomtraffic such as sequential page accesses or traffic which is focused onsmall number of blocks 206 within the storage device 104 may requireextra safety margins to be added to any values chosen. Selection of thevalue T is based on the minimum period during which large variations infocused traffic may occur, typically of the order of ¼ second, thereforea T of 100 ms might offer a good safety margin. Values greater than 1second increase the risk that focused traffic may cause the memory blockcounters 208 to hit their limits before sufficient checks have beenmade; values less than 100 ms may be largely unnecessary as the trafficvariations are unlikely to be conducted over such short periods.

For example, a storage device 104 may have a rated performancespecification of 1,000,000 IOPs. At 4 KB per IOP and a memory page of 4KB, if T is 100 ms, I*T is 100,000. If RDL=30,000 and SM=5,000,(RDL-SM)=25,000. Therefore N must be greater than 100,000/25,000, or 4.If T were chosen as 250 ms, a value of 16 may be chosen (>10).

Conventional systems use process 300 to manage memory blocks in a datastorage device as illustrated in FIG. 3. The process 300 begins byperforming a read operation on a memory block 206 in step 302. Forexample, SSD controller 106 can instruct the read-modify-write circuitry110 to perform a read operation on memory block 206 of NAND flash memory202.

Process 300 continues by decrementing a count 208 corresponding to thememory block 206 in step 304. For example, SSD controller 106 candecrement the value of count 208 in counter table 204 corresponding tothe memory block 206 of NAND flash memory 202.

Process 300 continues by determining whether a value of the count 208 isequal to zero in step 306. For example, SSD controller 106 can determinewhether the value of count 208 is equal to zero. If the value of thecount 208 is not equal to zero, process 300 continues to step 302.Otherwise, if the value of the count 208 is equal to zero, process 300continues to step 308.

Process 300 continues by determining an error level of data stored inthe memory block 206 in step 308. For example, SSD controller 106 candetermine an error level of data stored in the memory block 206 of NANDflash memory 202.

Process 300 continues by determining whether the error level of the datastored in the memory block 206 is above a threshold in step 310. Forexample, SSD controller 106 can determine if the determined error levelof the data stored in the memory block 206 of NAND flash memory 202 isabove the threshold error level. The threshold error level correspondsto an error level which is below the maximum error level that the SSDcontroller 106 can correct. If the error level of the data stored in thememory block 206 is not above the threshold error level, process 300continues to step 312. Otherwise, if the error level of the data storedin the memory block 206 is above the threshold error level, process 300continues to step 314.

Process 300 continues by incrementing the count 208 to a new limit instep 312. For example, SSD controller 106 can increment the value ofcount 208 in counter table 204 corresponding to the memory block 206 ofNAND flash memory 202 up to a new limit. The new limit may be the sameas a start limit or may be smaller than the start limit. For example, ifthe start limit is 30,000, the new limit may be 20,000. The new limitmay be based on the rate at which the SSD controller 106 determines thatthe error level of the data stored in the memory block 206 of NAND flashmemory 202 is above the threshold error level and the count 208corresponding to the memory block 206.

Process 300 continues by transferring the data to a secondary memoryblock 206 in step 314. For example, SSD controller 106 can transfer thedata stored in memory block 206 to a secondary memory block 206. Thesecondary memory block 206 may be a memory block 206 that is notcurrently storing data.

Process 300 continues by performing an erase operation on the memoryblock 206 in step 316. For example, SSD controller 106 can instruct theread-modify write circuitry 110 to perform an erase operation on thememory block 206 that had the error level above the threshold errorlevel.

Process 300 finishes by resetting the count 208 corresponding to thememory block 206 to a start limit in step 318. For example, SSDcontroller 106 can reset the value of count 208 in counter table 204corresponding to the memory block 206 of NAND flash memory 202 to astart limit.

After steps 306 and 312, process 300 proceeds to step 302 in order tocheck the error levels of the memory blocks 206 after each readoperation.

A process 400 of managing memory blocks in a data storage device usingcomputing system 100 is illustrated in FIG. 4. The process 400 begins byretrieving counts 208 from a counter table 204 in step 402. For example,SSD controller 106 can retrieve counts 208 from a counter table 204.

Process 400 continues by selecting a predetermined number of memoryblocks 206 corresponding to the lowest counts 208 in step 404. Forexample, SSD controller 106 can instruct search function circuitry 112to search for the memory blocks 206 of NAND flash memory 202 that havethe lowest counts 208 in counter table 204 and select the predeterminednumber of memory blocks 206 which have the lowest counts 208. Thepredetermined number of memory blocks 206 may correspond to the amountof memory blocks 206 _(N) that have data with read disturb errors withinan interval of T seconds. A large T will require a large predeterminednumber of memory blocks 206 and a small T will require a smallpredetermined number of memory blocks 206. The predetermined number ofmemory blocks 206 may range from four to sixteen as previouslyindicated, however, the choice may also be dependent on the processingcapability of the search function circuitry 112, where a smaller numberof N may be preferred for example, if the search function is implementedin firmware or software and not hardware. The search function will readthe counter table and collect the N minima in a bank of N registers.

Process 400 continues by determining the integrity of data in eachpredetermined number of memory blocks 206 in step 406. For example, SSDcontroller 106 can determine the error levels of each of thepredetermined number of memory blocks 206. The error levels of each ofthe predetermined number of memory blocks 206 may be determined when theSSD controller 106 performs a read operation on a memory block 206. Oncethe SSD controller 106 performs a read operation on one or more of pagesof the memory block 206, the SSD controller 106 can determine andcorrect any errors in the pages read from memory block 206 and candetermine the error levels of the memory block 206.

Process 400 continues by determining whether the error level of one ofthe predetermined memory blocks 206 is above a threshold in step 408.For example, for each of the predetermined memory blocks 206, the SSDcontroller 106 can determine whether the error level of the stored datain the memory block 206 is above the threshold error level. If the errorlevel of one of the predetermined memory blocks 206 is not above thethreshold, process 400 continues to step 410. Otherwise, if the errorlevel of one of the predetermined memory blocks 206 is above thethreshold, process 400 continues to step 412.

Process 400 continues by setting the count 208 to a new limit in step410. For example, for each of the predetermined memory blocks 206 witherror levels not above the threshold error level, SSD controller 106 canincrement the value of count 208 in counter table 204 corresponding tothe memory block 206 of NAND flash memory 202 up to a new limit. The newlimit may be the same as a start limit or may be smaller than the startlimit. For example, if the start limit is 30,000, the new limit may be20,000. The new limit may be based on the rate at which the SSDcontroller 106 determines that the error level of the data stored in thememory block 206 of NAND flash memory 202 is above the threshold errorlevel and the count 208 corresponding to the memory block 206.

Process 400 continues by transferring the data to a secondary memoryblock 206 in step 412. The transfer involves reading the data,correcting any errors, and writing the error corrected data to thesecondary memory block 206. For example, SSD controller 106 can transferthe data stored in memory block 206 to a secondary memory block 206. Thesecondary memory block 206 may be a memory block 206 that is erased andnot currently storing data.

Process 400 continues by performing an erase operation on the memoryblock 206 in step 414. For example, For example, SSD controller 106 caninstruct the read-modify write circuitry 110 to perform an eraseoperation on the memory block 206 that had the error level above thethreshold error level. If more than one memory block 206 had an errorlevel above the threshold error level, the SSD controller 106 caninstruct the read-modify-write circuitry 110 to perform an eraseoperation on all of the memory blocks 206 that had an error level abovethe threshold error level.

Process 400 finishes by resetting the count 208 to a start limit step416. For example, For example, SSD controller 106 can reset the value ofcount 208 in counter table 204 corresponding to the memory block 206 ofNAND flash memory 202 to a start limit. The start limit may be dynamicin order for the SSD controller 106 to consider the sensitivity of thememory block 206 to read disturb errors. The start limit may be based onthe rate at which the SSD controller 106 determines that the error levelof the data stored in the memory block 206 of NAND flash memory 202 isabove the threshold error level and the count 208 corresponding to thememory block 206. If more than one memory block 206 had an error levelabove the threshold error level, the SSD controller 106 can instruct theread-modify-write circuitry 110 to reset the value of the counts 208 incounter table 204 corresponding to all of the memory blocks 206 that hadan error level above the threshold error level.

After steps 410 and 416, process 400 proceeds to step 402 in order toperiodically check the error levels of the memory blocks 206 with thelowest counts 208.

FIG. 5 shows illustrative example representations 510, 520, 530, and540, each representing the values of counts 208 corresponding to memoryblocks 206 after different periods of process 400. Representation 510corresponds to an initial state of the counts 208. Representation 520corresponds to a 1^(st) state of the counts 208 after one period ofprocess 400. Representation 530 corresponds to a 2^(nd) state of thecounts 208 after two periods of process 400. Representation 540corresponds to a 3^(rd) state of the counts 208 after three periods ofprocess 400.

Representation 510 illustrates the values of counts 208 corresponding tomemory blocks 206 at an initial state. In this example, the initialstate of all of the counts 208 is the same. In other embodiments, theinitial state of all of the counts 208 may not be the same.

Representation 520 illustrates the values of counts 208 corresponding tomemory blocks 206 after one period of process 400. In this example, thememory block 206 corresponding to count 502 is checked for error levelsand the count 502 is incremented up to a new limit. Memory block 206corresponding to count 504 is not checked for error levels because apredetermined number of memory blocks 206 were already checked duringthe first period. In this example, four of the twelve memory blocks arechecked every period.

Representation 530 illustrates the values of counts 208 corresponding tomemory blocks 206 after two periods of process 400. In this example, thememory block 206 corresponding to count 504 is checked for error levelsand the count 504 is incremented up to a new limit. Memory blocks 206corresponding to count 502 and count 506 are not checked for errorlevels because a predetermined number of memory blocks 206 were alreadychecked during the second period. In representation 530, eight of thetwelve memory blocks 206 have had their count incremented after twoperiods of process 400.

Representation 540 illustrates the values of counts 208 corresponding tomemory blocks 206 after three periods of process 400. In this example,the memory block 206 corresponding to count 506 is checked for errorlevels and the count 506 is incremented up to a new limit. Memory blocks206 corresponding to count 502 and 504 are not checked for error levelsbecause a predetermined number of memory blocks 206 were already checkedduring the third period. In representation 540, all twelve of the memoryblocks 206 have had their count incremented after three period ofprocess 400.

In this example, after a fourth period of process 400, the memory blockcorresponding to count 502 is checked for error levels and the count 502is incremented up to a new limit because count 502 is included in thegroup of lowest counts 208.

Other objects, advantages and embodiments of the various aspects of thepresent invention will be apparent to those who are skilled in the fieldof the invention and are within the scope of the description and theaccompanying Figures. For example, but without limitation, structural orfunctional elements might be rearranged consistent with the presentinvention. Similarly, principles according to the present inventioncould be applied to other examples, which, even if not specificallydescribed here in detail, would nevertheless be within the scope of thepresent invention.

We claim:
 1. An SSD comprising: a non-volatile semiconductor memorydevice configured to store data in a plurality of memory blocks; and acontroller communicatively coupled to the non-volatile semiconductormemory device, configured to: for each memory block of the plurality ofmemory blocks, determine a number of remaining read operations, if any,capable of being performed; identify a first set of a plurality ofmemory blocks from the plurality of memory blocks, wherein each of theplurality of memory blocks in the first set has the number of remainingread operations capable of being performed less than the number ofremaining read operations capable of being performed on each memoryblock that is not identified in the first set; determine an error levelof each memory block of the first set, wherein, a number of memoryblocks in the first set is less than a total number of memory blocks inthe plurality of memory blocks and wherein the number of memory blocksin the first set is based on a predetermined criteria.
 2. The SSD ofclaim 1, wherein the predetermined criteria corresponds to a number ofmemory blocks with data with read disturb errors within a predeterminedtime period.
 3. The SSD of claim 1, wherein the predetermined criteriacorresponds to a rate of arrival of read requests from a hostcommunicatively coupled to the SSD.
 4. The SSD of claim 1, whereinpredetermined criteria corresponds an average number of the plurality ofmemory blocks with an error level above a predetermined threshold. 5.The SSD of claim 1, wherein the predetermined criteria is a fixednumber.
 6. The SSD of claim 1, wherein the predetermined criteriacorresponds to a size of each of a plurality of IO operations.
 7. TheSSD of claim 1, wherein is the predetermined criteria corresponds to apage size of the memory blocks.
 8. The SSD of claim 1, wherein thepredetermined criteria corresponds to a number of read operationsreceived in a predetermined time period.
 9. The SSD of claim 1, whereinif the error level of a memory block of the first set satisfies athreshold, then: read data stored in the memory block; error correct thedata read from the memory block; and store the error corrected data in asecond memory block.
 10. The SSD of claim 1, wherein if the error levelof a memory block of the first set does not satisfy a threshold, thecontroller is further configured to increase the number of remainingread operations capable of being performed on the memory block to apredetermined number.
 11. A method of managing an SSD, the methodcomprising: determining a number of remaining read operations, if any,capable of being performed on each memory block of a plurality memoryblocks; identifying a first set of a plurality of memory blocks from theplurality of memory blocks, wherein each of the plurality of memoryblocks in the first set has the number of remaining read operationscapable of being performed less than the number of remaining readoperations capable of being performed on each memory blocks that is notidentified in the first set; and determining the error level of eachmemory block of the first set, wherein, a number of memory blocks in thefirst set is less than a total number of memory blocks in the pluralityof memory blocks and the number of memory blocks in the first set isbased on a predetermined criteria.
 12. The method of claim 11, whereinthe predetermined criteria corresponds to a number of memory blocks withdata with read disturbs errors within a predetermined time period. 13.The method of claim 11, wherein the predetermined criteria correspondsto a rate of arrival of read requests from a host communicativelycoupled to the SSD.
 14. The method of claim 11, wherein thepredetermined criteria corresponds to an average number of the pluralityof memory blocks with an error level above a predetermined threshold.15. The method of claim 11, wherein the predetermined criteria is afixed number.
 16. The method of claim 11, wherein the predeterminedcriteria corresponds to a size of each of a plurality of TO operations.17. The method of claim 11, wherein is the predetermined criteriacorresponds to a page size of the memory blocks.
 18. The method of claim11, wherein the predetermined criteria corresponds to a number of readoperations received in a predetermined time period.
 19. The method ofclaim 11, wherein if the error level of a memory block of the first setsatisfies a threshold, then: reading data stored in the memory block;error correcting the data read from the memory block; and storing theerror corrected data in a second memory block.
 20. The method of claim11, wherein if the error level of a memory block of the first set doesnot satisfy a threshold, increasing the number of remaining readoperations capable of being performed on the memory block to apredetermined number.